In semiconductor memories of this type, a nitride layer is often used as the charge-storing level and is surrounded on both sides by a thin oxide layer, for example, of silicon dioxide. In this three-layer sequence, the nitride layer and the oxide layers are in each case very thin; their layer thicknesses are typically a few dozen nanometers. In at least one of the oxide layers, a tunneling mechanism is used where charge carriers are accelerated between two electrodes in the lateral direction parallel to the substrate surface in channel regions of transistor structures. Just before the charge carriers reach the target electrode, some charge carriers reach such a high energy that, as a result of scatter effects, the charge carriers can be scattered through a thin oxide layer arranged on the substrate surface and as a result penetrate into a layer arranged above. Provided that a nitride layer, which retains the charges in a spatially fixed position is arranged above the oxide layer, this tunneling mechanism can be put to technological use to permanently store a digital information item in, for example, a silicon nitride layer. Charge quantities can be stored in localized form, in particular, above edge regions of electrodes arranged in the substrate, where the high-energy electrons (hot channel electrons) reach their highest kinetic energy. Since a nitride layer spatially retains scattered-in charge carriers and prevents them from migrating through the nitride layer, at least if the temperature is not excessively high, two independent digital information items can be stored in a nitride layer, for example, above two pn junctions of a field-effect transistor.
Therefore, the nitride layer in an oxide-nitride-oxide arrangement of layer forms a trapping layer, i.e., a layer which retains scattered-in charges. To store a digital information item, a sufficiently large number of charge carriers, for example electrons or defect electrons, have to be scattered into the charge-storing level in a spatially concentrated form. A digital information item of this type is erased by introduction of the opposite type of charge carrier. In the case of a digital information item formed from scattered-in charge carriers, this information item is erased by the introduction of defect electrons, and vice versa. The alternate scattering-in of electrons and defect electrons is effected by adjustment of the potentials of the electrodes.
If store, erase, and charge reversal operations are carried out repeatedly, electrons and defect electrons, which are scattered into the charge-storing level through the tunnel barrier layer, may not recombine. Instead, a certain quantity of electrons and defect electrons remains in the charge-storing level and these electrons and defect electrons recombine with one another at elevated temperatures, such as in tests to simulate ageing phenomena after long-term storage for a number of years.
The cause of the electrons and defect electrons remaining in the charge-storing level is different lateral density distributions of the scattered-in electrons and of the scattered-in defect electrons with respect to the substrate surface. Since the electrical potentials of source/drain electrodes and gate electrodes required to scatter-in defect electrons are different than in the case of scattered-in electrons, the position of the scattered-in defect electrons in the xy plane of the nitride layer with respect to the substrate surface is different than in the case of the electrons. As a result, in the event of an erase or charge reversal operation, a certain proportion of the scattered-in charge quantity is erased or written over. As a result, the storage properties of the integrated semiconductor memory gradually deteriorate, and increases in temperature can lead to a sudden, at least partial loss of charge, i.e., to a loss of the stored digital information item. Moreover, the net charge formed by the sum of the scattered-in electrons and defect electrons and consequently also the long-term storage capacity of the semiconductor memory are reduced.
It has in some instances been proposed to laterally pattern the arrangement of layers, in order to restrict the region in which electrons and defect electrons can penetrate into the charge-storing level in the lateral direction parallel to the substrate surface. However, this would require lithographic process steps, which would increase the work involved and the costs entailed by the fabrication of the integrated semiconductor memory. Furthermore, it has been proposed to increase the long-term storage capacity of the semiconductor memory by incorporating nanocrystals of semiconducting material, such as, for example, silicon or germanium, in the charge-storing level. In this case, however, the charge carriers are retained by potential differences with respect to the matrix dielectric.
A nonvolatile integrated semiconductor memory with a reduced risk of the recombination of electrons and defect electrons, which have remained in the charge-storing level after repeated reprogramming and which has a higher long-term storage capacity, is desirable.